In modern high density memories, such as random access memories having 2.sup.20 bits (1 Megabit) or more, the time and equipment required to test functionality and timing of all bits in the memory constitutes a significant portion of the manufacturing cost. Accordingly, as the time required for such testing increases, the manufacturing costs also increase. Similarly, if the time required for the testing of the memory can be reduced, the manufacturing cost of the memories is similarly reduced. Since the manufacturing of memory devices is generally done in high volume, the savings of even a few seconds per device can result in significant cost reduction and capital avoidance, considering the high volume of memory devices produced.
Random access memories (RAMs) are especially subject to having significant test costs, not only because of the necessity of both writing data to and reading data from each of the bits in the memory, but also because RAMs are often subject to failures due to pattern sensitivity. Pattern sensitivity failures arise because the ability of a bit to retain its stored data state may depend upon the data states stored in, and the operations upon, bits which are physically adjacent to a particular bit being tested. This causes the test time for RAMs to be not only linearly dependent upon its density (i.e, the number of bits available for storage) but, for some pattern sensitivity tests, dependent upon the square (or 3/2 power) of the number of bits. Obviously, as the density of RAM devices increases (generally by a factor of four, from generation to generation), the time required to test each bit of each device in production increases at a rapid rate.
It should be noted that many other integrated circuit devices besides memory chips themselves utilize memories on-chip. Examples of such integrated circuits include many modern microprocessors and microcomputers, as well as custom devices such as gate arrays which have memory embedded therewithin. Similar cost pressures are faced in the production of these products as well, including the time and equipment required for testing of the memory portions.
A solution which has been used in the past to reduce the time and equipment required for the testing of semiconductor memories such as RAMs is the use of special "test" modes, where the memory enters a special operation different from its normal operation. In such test modes, the operation of the memory can be quite different from that of normal operation, as the operation of internal testing can be done without being subject to the constraints of normal operation.
An example of a special test mode is an internal "parallel", or multi-bit, test mode. Conventional parallel test modes allow access to more than one memory location in a single cycle, with common data written to and read from the multiple locations simultaneously. For memories which have multiple input/output terminals, multiple bits would be accessed in such a mode for each of the input/output terminals, in order to achieve the parallel test operation. This parallel test mode of course is not available in normal operation, since the user must be able to independently access each bit in order to utilize the full capacity of the memory. Such parallel testing is preferably done in such a way so that the multiple bits accessed in each cycle are physically separated from one another, so that there is little likelihood of pattern sensitivity interaction among the simultaneously accessed bits. A description of such parallel testing may be found in McAdams et al., "A 1-Mbit CMOS Dynamic RAM With Design-For-Test Functions", IEEE Journal of Solid-State Circuits, Vol SC-21, No. 5 (October 1986), pp. 635-642.
As described in this article, conventional parallel test operations may be done in one of two ways. A first one of these methods merely compares the data state read from each of the multiple simultaneously accessed bits with one another. If all of the simultaneously accessed bits have the same data, the test operation passes. A second method for parallel test, commonly referred to as "expected data parallel test", is performed by comparing the data presented by the accessed bits against one another, and also against the contents of an on-chip register to determine not only that the same data was read from all accessed bits, but also that the data state read was the correct data state.
For either case, the internal comparison of multiple sensed data states must be performed on-chip, with the results communicated externally therefrom. In the McAdams et al. article cited hereinabove, relative to its FIG. 8, a multiple stage comparator is provided which receives internal data lines DL0 through DL7 and performs a comparison among the same (and with expected data ED if desired). In this example, however, each internal data line is connected to both an input of a NAND function and also an input of an OR function. It is therefore contemplated that the internal data line loading presented by the parallel comparator described in the McAdams et al. article is significant, and will slow the performance of the internal read path during normal operation. Furthermore, the layout area required for the comparator of the McAdams et al. article (including eleven logic functions, one of which is an exclusive-OR), is believed to be substantial.
By way of further background, U.S. Pat. Nos. 4,654,849 and 4,860,259 describe other parallel test schemes. The multiple bit comparators disclosed in these references (see FIGS. 1 and 8 of U.S. Pat. No. 4,654,849, and FIGS. 4A and 7B of U.S. Pat. No. 4,860,259) are each configured as static logic gates, similarly as in the McAdams et al. article, and are thus believed to suffer from similar increases in internal data bus loading and the resulting performance degradation in normal operation, and also from significant layout and chip area pressures.
Another known technique for performing an internal parallel comparison in test mode is described in Shimada et al., "A 46-ns 1-Mbit CMOS SRAM", IEEE Journal of Solid-State Circuits, Vol. 23, No. 1, (Feb. 1988) pp. 53-58. As described in this article relative to its FIG. 5, parallel test is accomplished in this device by the simultaneous access of four of the array blocks. The comparison of the data retrieved from the four accessed bits is accomplished by arbiter buffers, which drive lines BUS and BUS.sub.-- in wired-AND fashion. As noted on page 55, since the p-channel pull-up transistors in the arbiter buffers are small, if any of the four selected cells fails (e.g., has a "0" instead of a "1"), both of lines BUS and BUS.sub.-- will be at a low logic level. The operation of the NAND gates will, in such a case, will provide a "1" input to both of the NORs driving the pull-up and pull-down transistors of the output buffer, forcing a high-impedance state at the output of the device.
As is evident from this construction, however, it is apparent that the arbiter buffers are connected in series in the data path between the sense amplifiers and the data out terminal both for normal and parallel test modes. Accordingly, the propagation delay required by the arbiter buffers is also seen during normal operation, so that an access time penalty is paid in order to implement the parallel test comparison. This penalty is made worse by the construction of the arbiter buffers in such a way that the p-channel pull-up transistors are sufficiently small so that a single n-channel pull-down transistor (in the example of a test failure due to reading a "0" instead of a "1") can pull down line BUS or BUS.sub.-- which is being pulled high by the other three p-channel transistors. This small size for the pull-up devices will, of course, result in a slow transition time for a line BUS or BUS.sub.-- going from a low to a high logic level for a read operation. Furthermore, the slow transition time will become even worse if the parallel test design goes from a by-four test to a by-eight or wider parallel test operation, since a single n-channel transistor must be capable of pulling down a node being pulled up by seven, or fifteen in the case of a by-sixteen test, p-channel pull-up transistors. Accordingly, the scheme described in the Shimada et al. paper will become less useful for wider parallel test operations. Of course, as memories become larger and larger, it will become desirable to test even more bits in parallel.
By way of further background, copending application Ser. No. 552,567, filed Jul. 13, 1990, assigned to SGS-Thomson Microelectronics, Inc., and incorporated herein by this reference, describes a static random access memory (SRAM) including a parallel test mode; the results of the parallel test are communicated at the data output terminals, with a high-impedance state indicating a failed parallel comparison for a particular input/output. The SRAM device described in this copending application utilizes a series of comparators for comparing multiple internal data lines in a parallel test mode. As described relative to FIG. 3 of copending application Ser. No. 552,567, pairs of data words are compared in bit-by-bit fashion by a series of comparators, with a final signal generated according to the results of the comparison, and coupled to the output drivers.
It is an object of the present invention to provide a memory having a parallel test mode which presents minimal loading to internal data bus lines.
It is a further object of the present invention to provide such a memory which includes a parallel test multiple-bit data comparator which is outside of the internal data path in normal operation.
It is a further object of the present invention to provide such a memory which presents minimal propagation delay in the parallel test multiple-bit comparison.
It is a further object of the present invention to provide such a memory which may be efficiently laid out in relatively small chip area.
Other objects and advantages of the present invention will be apparent to those of ordinary skill in the art having reference to the following specification together with the drawings.